High-level Model for designing reliable RISC-V architecture for autonomous vehicle

The postdoctoral researcher will work on methodologies for evaluating processor reliability and dependability in compliance with automotive industry requirements. The purpose of this work is to define a high level model for the design of reliable architecture supporting autonomous automotive applications requirement. In the Rigoletto project application, we will focus on open-hardware processor based on the RISC-V ISA. The model will be used to define a methodology and tools to explore architecture so as to find a tradeoff between reliability, and performances (speed, area, …). The main applications domain is focused on AI and ML accelerators. The position requires in-depth knowledge of RISC-V architectures and proficiency in modeling tools (such as Gem5) to assess performance, reliability, and energy trade-offs. Skills in system reliability (ECC codes, fault detection, redundancy) and the development of custom tools or scripts (Python, C++) for simulation and test campaign automation are essential. Understanding on AI and ML models will be an asset.