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Evaluation of the robustness of ML algorithms executed on a non-hardened accelerator through circuit-level fault-injection
The project addresses the challenges of deploying AI applications on Commercial-Off-The-Shelf (COTS) components in the space domain, a growing trend within the so-called new-space movement. While COTS technologies offer significant performance and cost advantages, they lack radiation hardening and are therefore highly susceptible to transient hardware faults (e.g., radiation-induced bit flips).
The goal is to explore fault tolerance co-design strategies (hardware and software) that ensure predictable timing, performance, and safety for AI workloads running on a new space platform. The project relies on the POMELOS platform [1] and the SPARROW accelerator [2], a specialized hardware accelerator designed for efficient CNN execution on ARM-based COTS processors.
The recruited researcher will focus on the evaluation of the robustness of ML algorithms executed on an ARM-based new space platform integrating the SPARROW accelerator through circuit-level fault injection. The main objectives are:
Define a representative fault model for the SPARROW accelerator.
Develop methods to instrument the HDL code of SPARROW (e.g., with logic gates and multiplexers) to simulate transient faults, ideally through automated insertion.
Conduct fault injection campaigns on the target hardware platform to evaluate the impact of transient faults on CNN accuracy and robustness.
Propose new fault-tolerance co-design strategies to improve dependablity of new space systems
The results will help characterize how faults propagate through the system and distinguish between minor, tolerable faults and critical ones requiring mitigation.
[1] POMELOS SpaceTechDroneTech CPER platform, at http://beru.univ-brest.fr/pomelos
[2] Bonet, M. S., & Kosmidis, L. (2022, March). SPARROW: a low-cost hardware/software co-designed SIMD microarchitecture for AI operations in space processors. In 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 1139-1142). IEEE.
Candidates must have obtained their PhD in computer science or electronics with a specialization in embedded systems or hardware design within the last three years.
· Solid background in hardware design and verification (HDL: VHDL/Verilog, simulation tools).
· Hands-on experience with FPGA prototyping or hardware/software co-design is highly desirable.
· Good communication skills in English (required), as project meetings will be conducted in English.
Additional assets (not mandatory):
· Knowledge of fault injection techniques or hardware reliability.
· Understanding of hardware accelerators for AI and their operation.
· Familiarity with machine learning workloads (e.g., CNNs).
As this is a research position, it is necessary to be able to work in a team, write state-of-the-art reports, and write scientific articles.